Static random access memory (“SRAM”) arrays are commonly used for storage on integrated circuit devices. Recent advances in finFET transistor technology have made advanced SRAM cells using finFET transistors possible. In contrast to the prior planar MOS transistor, which has a channel formed at the surface of a semiconductor substrate, a finFET has a three dimensional channel region. In the finFET, the channel for the transistor is formed on the sides, and sometimes also the top, of a “fin” of semiconductor material. The gate, typically a polysilicon or metal gate, extends over the fin and a gate dielectric is disposed between the gate and the fin. The three-dimensional shape of the finFET channel region allows for an increased gate width without increased silicon area, even as the overall scale of the devices is reduced with semiconductor process scaling and in conjunction with a reduced gate length; providing a reasonable channel width characteristic at a low silicon area cost.
However, when an SRAM cell is formed using single fin finFET transistors for the pull up or “PU” transistors and also the pass gate “PG” transistors, the “alpha ratio” of the on current (“Ion”) for the PU and PG transistors, that is the ratio PU_Ion/PG_Ion, is negatively impacted. The SRAM cells formed of these transistors may therefore exhibit a poor write margin metric, and the amount that the cell positive supply voltage Vcc can be lowered (“Vcc_min”) while maintaining proper operation will be reduced. A reduced Vcc_min metric negatively impacts the power consumption for an integrated circuit using the SRAM cells. In the known approaches, solutions such as threshold voltage (“Vt”) tuning and gate length skew adjustments of certain ones of the finFET devices are used to increase performance of the SRAM cells. However, these approaches suffer from additional lithography or added ion implants, increase costs in the manufacturing process, and may create critical dimension or cell size concerns.
In some applications the primary goal of an SRAM array for use in an integrated circuit is the silicon area used per stored bit, which needs to be reduced as much as possible. However, in cases when SRAM storage is used for high speed data access, as in cache storage for a microprocessor such as level one (“L1”) or level two (“L2”) on-board cache, access speed is also very important. For these GHz speed cache SRAMs the cells may be formed of larger width transistor devices in order to increase the transistor drive currents and operation speed. Use of Vt or other process adjustments now used to provide these devices with higher drive current creates additional processing costs and manufacturing problems.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.